Moore’s law states that the density of transistors in an integrated circuit (IC) doubles about every two years. This empirical law has allowed the manufacturing of cheaper, faster, smaller and more efficient electronic devices for decades.
But the pace of this trend is clearly slowing down and the techniques to miniaturize transistors are getting exponentially expensive. For example, the next generation of machines performing the critical lithographic process that engraves the chips’ designs on silicon (Hyper-NA Extreme Ultraviolet) are rumored to cost more than $700 million apiece (vs. $200 million for the current generation)!
As the 2D transistors’ shrinking process is slowing down and its related costs are shooting to the roof, the semiconductor industry has now taken the 3D route by vertically stacking transistors inside chips. 3D ICs are therefore becoming one of the main solutions to “artificially” sustain Moore’s law as the number of transistors keeps on increasing while the chips’ footprint stays the same.
However, the manufacturing of 3D ICs brings many new challenges, one of them being the ability to realize vertical electric connections (bonds) to connect the chips’ layers together. The semiconductor industry is converging towards a technology called hybrid bonding, which consists of stacking one wafer (or die, a silicon piece) directly on top of another one. Between these two wafers/dies lies a very fine isolating layer (dielectric) with a very high dense pattern of copper pads. This technique enables linking the whole silicon “sandwich” together with performances close to monolithic chips in terms of electric consumption, bandwidth and signal integrity.
Hybrid bonding, considered by some experts as the most transformative innovation in semiconductor manufacturing since Extreme Ultraviolet lithography, imposes very stringent requirements: a perfect wafer surface smoothness, cleanliness and flatness as well as high alignment accuracy to achieve defect-free bonds. All of those constraints make hybrid bonding extremely sensible to particles, hence requiring advanced cleanrooms which are usually used in “front-end” processes.
As hybrid bonding is a technology that requires an environment similar to semiconductor fabs, the traditional packaging players (called OSATs, Outsourced Semiconductor Assembly and Test) are, for the moment, left out of this trend. Currently, the lion’s share of hybrid bonded 3D chips is controlled by the usual suspects, Intel, TSMC, Samsung, SK Hynix, Micron… as they operate the state-of-the-art fabs where the most complex 3D chips, requiring this advanced bonding technology, are manufactured.
As the hybrid bonding process requires specific tools and equipment, a pick-and-shovel strategy is, in our view, the best way to get exposure to this critical technology.
As mentioned above, wafers’ need to be perfectly flat in order for the tiny copper pads to perfectly fit and hence connect the two silicon layers. This very high precision polishing step is realized by machines performing chemical mechanical planarization (CMP). The connecting pads themselves are created by copper electrodeposition while the cutting of the dies must be realized with plasma dicing machines to keep the number of particles close to zero.
Several companies (both private and listed) based in Europe, the US, Korea and Japan are involved in the various stages of the hybrid bonding process. These players are selling the (hybrid) bonding machines themselves, advanced packaging tools, inspection and metrology equipment, as well as CMP and dielectric deposition solutions.
Hybrid bonding is still an expensive process used exclusively for high-end chips. This could change in the coming years as very promising Chinese players are entering the field. Some of them (listed companies) have been already able to produce HBM-type memory chips with 3D packaging and hybrid bonding techniques. This will, without doubt, lower the costs to the point where mainstream applications could also benefit from this top-notch manufacturing technology. It seems that this future is not too far away as rumors have that Apple is already considering TSMC’s SoIC technology for the chips that will power its devices in 2025.
The demand for advanced packaging equipment will stay at very elevated levels in the coming years as AI is literally pushing the secular innovative trend of the whole semiconductor industry towards new limits. Furthermore, the upcoming chiplet era – where heterogeneous chips will be packaged together – is another strong driver to sustain this race that has just started and will result into chips packing more than 1 trillion transistors by the end of the decade.
Importantly, these technologies rely on a rich ecosystem of suppliers (largely based in Asia), providing many investment opportunities.
